Mechanism for storing and extracting trace information using internal memory in microcontrollers

ABSTRACT

It is the object of the present invention to provide a mechanism to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. The on-chip debug logic includes a low speed debug port and a mechanism for temporarily storing trace data on the memory, wherein the trace data can be retrieved via the low speed debug port by a debug tool. A method and system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

FIELD OF THE INVENTION

The present invention relates generally to on-chip debug functionalityin microcontrollers and microprocessors that contain on-chip memory andmore specifically to storing trace information in and extracting suchinformation from on-chip memory.

BACKGROUND OF THE INVENTION

FIG. 1 shows a conventional debug system 10 with direct memory accessand trace support. The debug system 10 comprises a host computer 12, adebug tool 14, a low speed debug interface 16, a high speed tracecapture and processing unit 18, a low-speed debug port 15, a high-speedtrace port 17, a microcontroller device 20 and a system memory 36. Themicrocontroller device 20 includes an on-chip debug logic 22, a framebuffer 24, an on-chip debug control 26, a bus monitor 28, a memoryinterface 30, a CPU 32 and a bus matrix 34. Traditionally, electronicsystems with advanced control or data processing requirements wouldcontain separate CPU 32 and memory devices, soldered onto the sameprinted circuit board. During developing and debugging embeddedsoftware, it was thus possible to use logic analyzers to probe thesystem bus to identify and capture events useful for software debugging.With the advent of powerful microcontrollers with on-chip memories, thesystem bus resides within the device, and the bus events are no longeravailable for direct capture. The problem becomes particularlynoticeable as microcontrollers become ever more complex, with acorresponding increase in software complexity. As many embedded systemsinvolve real-time communication, control, or data processing, thedebugging task becomes further complicated, as more debug features haveto be non-intrusive, i.e., not disrupt the real-time software execution.

To avoid software development time increasing exponentially, on-chipdebug (OCD) logic 22 is required to assist in observing and controllingthe embedded processor through a set of debug features. A debug tool 14interfaces between the development software on a host computer 12 andthe OCD logic 22 through a debug port 15 (e.g. JTAG) and a trace port17.

The most basic debug features involve intrusive control of CPU 32operation. This includes breakpoints, to selectively halt the CPU 32based on a specific condition, and methods to examine the CPU 32registers and restart the CPU 32 to normal operation. These debugfeatures are normally controlled by a set of debug registers, accessiblethrough a debug interface, e.g., JTAG. As all real-time events arehandled by the OCD logic 22, the debug tool 14 does not have to containhigh-speed logic, and can be designed in a simple, low-cost fashion.

The basic debug features allow intrusive debug access to system memory36 by halting the CPU 32, and issuing instructions to examine or alterthe system memory 36. However, with the increasing complexity ofembedded real-time systems, non-intrusive direct memory access to systemmemory 36 has become a requirement (e.g. Nexus 2.0 standard, IEEEISTO5001™-2003, class 3). This enables the debug tool 14 to use thelow-speed debug port 15 to observe and alter memory without requiringthe CPU 32 to be halted.

More advanced are trace features, which replace the traditional logicanalyzers, and thus constitute an important part of on-chip debugging incomplex microcontroller applications. This involves reconstructing theprogram or data flow of the embedded software to identify the point ofincorrect program execution. This is accomplished by logging a sequenceof characteristic debug events, collectively known as trace information,such as program branches, and system bus accesses, during the softwareexecution. Data is supplied with each event to relate the event to theexecution, allowing the exact execution sequence to be reconstructed.

Trace information is formatted into messages, consisting of frames,corresponding to one set of data on the trace port 17 of the device. Thetrace information is generated in bursts, resulting in a very high peakframe rate. The average frame rate is usually much lower, and it istherefore economical to keep the generated frames in a frame buffer 24,and transmit them through the trace port 17 at a frame rate closer tothe average frame rate. The trace information can then be captured,stored, and analyzed by the debug tool 14.

The trace features are nevertheless very bandwidth intensive. The framebuffer 24 and dedicated trace port 17 add to the cost of themicrocontroller 20. The high bandwidth also strongly increases the costof the debug tool 14, which requires complex and expensive hardware tocapture and process the vast amount of high-speed trace information.

The trace frames are normally stored in a large buffer within the debugtool 14, allowing for a relatively long real-time trace sequence to becaptured. However, many software debug situations do not require theentire trace sequence, only the first messages (e.g. exit from aninterrupt handler), or last messages (e.g. illegal entry to a trap).Thus, trace implementations with a limited trace buffer would still behighly valuable.

Accordingly, what is needed is a system and method for lowering the costof implementing trace features both for the microcontroller and for thedebug tools. The present invention addresses such a need.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide a mechanism tostore and retrieve trace information in on-chip system memory ofmicrocontrollers. A microcontroller comprises a microprocessor and amemory device accessible through a data bus and an address bus coupledto the microprocessor. The microcontroller includes on-chip debug logiccoupled to the microprocessor. The on-chip debug logic includes a lowspeed debug port and a mechanism for temporarily storing trace data onthe memory, wherein the trace data can be retrieved via the low speeddebug port by a debug tool.

A method and system in accordance with the present invention will lowerthe cost of implementation of trace features in microcontrollers, andstrongly reduce the cost of supporting such features in debug tools.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional debug system with direct memory access andtrace support.

FIG. 2 illustrates a debug system in accordance with the presentinvention.

FIG. 3 illustrates the debug system with an expanded view of the traceextractor module and the system memory.

FIG. 4 shows RWD register organization.

FIG. 5 shows reconstructing a message from the trace buffer.

DETAILED DESCRIPTION

The present invention relates generally to on-chip debug functionalityin microcontrollers and microprocessors that contain on-chip memory andmore specifically to storing trace information in and extracting suchinformation from on-chip memory. The following description is presentedto enable one of ordinary skill in the art to make and use the inventionand is provided in the context of a patent application and itsrequirements. Various modifications to the preferred embodiments and thegeneric principles and features described herein will be readilyapparent to those skilled in the art. Thus, the present invention is notintended to be limited to the embodiments shown, but is to be accordedthe widest scope consistent with the principles and features describedherein.

The present invention presents a mechanism for storing trace events insystem memory and allowing them to be extracted over the low-speed debugport in the device.

The present invention includes an implementation of an on-chip tracebuffer and a frame buffer, as well as a memory interface fornon-intrusive memory access. Frames are extracted from the buffer androuted to the memory interface, to be stored in a circular trace bufferin system memory, instead of transmitted on a trace port. The positionand size of the trace buffer in system memory are configured by debugregisters, accessible by a debug tool. In a preferred embodiment, thehigh-speed trace port is eliminated, and the frame buffer can be reducedin size, as the bandwidth of the memory interface is close to the peakframe rate.

The trace sequence that can be captured is much smaller than when usingan external debug tool for trace capture, since the trace buffer islimited to the size of the allocatable internal memory. However, asstated above, many debug situations do not require a large tracesequence, if the user can control which sequence is captured. In asystem and method in accordance with the present invention, the user ispresented with several options when the trace buffer becomes full:

1. Continue writing at the start of the buffer, overwriting the oldestframes.

2. Stop writing, discarding any further frames generated.

3. Halt the CPU automatically, to avoid further messages to begenerated.

In any case, the debug tool can at any time halt the CPU explicitly,which prevents further trace information from being generated. The debugtool can subsequently extract the previous trace information by readingout the trace buffer from system memory, without any specific bandwidthrequirement. Also, the regular debug port can be used to extract theinformation, eliminating the need for a dedicated trace port. Inaddition, mechanisms are provided to identify the portion of the buffercontaining valid frames, and to extract remaining frames not yet writtento the buffer. Finally, mechanisms are also provided to protect the CPUfrom accessing the system memory area reserved for the trace buffer, toprevent incorrect trace reconstruction.

To describe the features of the present invention in more detail refernow to the following description in conjunction with the accompanyingfigures.

FIG. 2 illustrates a debug system 100 in accordance with the presentinvention. The debug system 100 comprises a host computer 12′, a debugtool 114, a microcontroller device 120 and system memory 36′. Themicrocontroller device 120 includes on-chip debug logic 12, CPU 32′ anda bus matrix 34. Although system memory 36′ is shown on-chip here, thememory can reside on-chip or off-chip depending on the implantation ofthe microcontroller device. The on-chip debug logic 121 comprises atrace extractor module 122, a trace buffer protect module 129, a framebuffer 124, an on-chip debug control 126, a bus monitor 128, and memoryinterface 130. In this architecture, the trace extractor module 122 isadded to on-chip debug logic 121 provide a mechanism for storing traceevents without adding significant cost to the microcontroller device120. The trace extractor module 122 is an extension of the memoryinterface, and contains a plurality of debug registers, which can bewritten by the debug tool 114, and that configure the behavior of theon-chip memory trace mechanism. To describe the function of the traceextractor module 122 in more detail refer now to the followingdescription in conjunction with the accompanying figure.

FIG. 3 illustrates the debug system 100 with an expanded view of thetrace extractor module 122 and the system memory 36′. FIG. 3 comprises aframe buffer 124, on-chip debug control 126, bus monitor 128, CPU 32′,bus matrix 34′, memory interface 130, and trace extractor module 122.The trace extractor module 122 comprises a trace buffer 122, a RWDregister 202, CNT register 204, trace buffer access protection 206, aRWA register 208, status registers 210 and a plurality of controlregisters 212.

As before mentioned, the trace extractor module 122 includes a pluralityof debug registers which can be written by the debug tool 114. Theregisters can be summarized as follows:

RWA register 208: An automatically incremented register, reflecting thenext system memory address to be written.

RWD register 202: a register collecting frames into bus-sized units.

CNT register 204: the logarithmic size of the trace buffer.

Control register 212: a control register indicating the actions takenwhen the trace buffer is full. Valid states are WRAP, STOP, and BREAK.

Status registers 210: a plurality of single-bit read-only registersindicating the status of the trace buffer 206.

The following definitions describe the status of the trace buffer 206:

WRAPPED: The trace buffer 206 has been overwritten, and old messageshave been discarded.

NTBF: A breakpoint has been issued due to the trace buffer 206 beingfull.

NTAE: A breakpoint has been issued due to the CPU 32′ trying to accessthe trace buffer 206.

Referring further to FIG. 3, the debug tool 114 reserves a portion ofsystem memory 36′ for the trace buffer 206 by writing the RWA register208 to the START_ADDRESS, and writing the CNT register 204 with thelogarithmic buffer size, creating a bufferEND_ADDRESS=(START_ADDRESS+2^(CNT)−1). The implicit address unit used isthe system bus access width, e.g. word=32 bits.

The trace extractor module 122 accumulates frames from the frame buffer124 into the RWD register 202, which is the same width as the systemdata bus. This register 202 collects frames until full, e.g., if theframe size is 8 bits, and the data bus 32 bits, the RWD register 202 canhold 4 frames.

When RWD 202 is full, the contents of the register are written throughthe memory interface 130 to the system memory 36′ address pointed to bythe RWA register 208. After this operation, the RWA register 208 isauto-incremented to point to the next location in the buffer. The RWDregister 202 is cleared, i.e., filled with only empty frames.

When RWA 208 increments beyond END_ADDRESS, the MODE register definesthe resulting behavior:

In a=WRAP mode: the RWA register 208 is reset to START_ADDRESS, and thetrace buffer 206 is overwritten without halting the CPU 32′. The WRAPPEDstatus bit is set. The debug tool 114 must halt the CPU 32′ beforereconstruction of trace data can begin. The captured trace data willcontain the last frames before the CPU 32′ was halted.

In a=STOP mode: No further trace frames are written to system memory36′, but the CPU 32′ is not halted. The debug tool must halt the CPU 32′before reconstruction of trace data can begin. The captured trace datawill contain the first frames after the capture sequence was started.

In a=BREAK mode: No further trace frames are written to system memory36′, and the CPU 32′ is halted. The NTBF status is set, to identify thisbreakpoint. Reconstruction of the trace frames can commence immediately.The captured trace data will contain all frames after the capturesequence was started.

Once the CPU 32′ is halted, regardless of reason for the breakpoint, thedebugger can read out the valid trace frames from the system memory 36′using the low speed debug port 15 and the memory interface 130.

The location of valid frames in the trace buffer 206 depends on whetherthe circular trace buffer in system memory 36′ was overwritten or not,as indicated by the WRAPPED status bit. The WRAP status bit has thefollowing states:

WRAPPED=0: The trace buffer 206 contains valid trace frames fromSTART_ADDRESS through (RWA-1).

WRAPPED=1: The trace buffer 206 contains valid trace frames fromEND_ADDRESS plus START_ADDRESS through (RWA-1).

EXAMPLE

Assuming an implementation using 8-bit Nexus-compatible frames (2-bitMSEO control and 6-bit MDO data), and a big-endian 32-bit system bus,the RWD register 202 will be organized as shown in FIG. 4. Accordinglythis register collects frames into bus-sized units.

FIG. 5 shows reconstructing a message from the trace buffer 206 (FIG.3). In this example a message from the trace buffer 206 is shown afterthe CPU 32′ has been halted, with the RWA register 208 starting at0x1000 and the CNT register=10 (i.e. the buffer size is 1024 words, or4096 frames). When the trace was stopped, the WRAPPED status bit is setand the RWA register 208=0x 1234, so the last word of frame data writtento the memory is located at 0x1230. The last two frames of the messagestill reside in the RWD register 202, which has been only partiallyfilled.

If the RWD register 202 was not full by the time the breakpointoccurred, these frames are not written to the trace buffer 206. If thedebug tool intends to read out the trace buffer 206, the last frames canbe found by reading the RWD register 202, after reading out to the tracebuffer 206.

If the debug tool 114 does not intend to read out the trace buffer 206,e.g. due to a non-trace-related breakpoint, it can let the CPU 32′return to normal operation, and the trace operation will continue,transparently to the debug tool 114.

The mechanism described above assumes that the system memory 36′ is ashared resource between CPU and OCD logic. This means that a softwareerror in the CPU 32′ can potentially corrupt the trace data byaccidentally writing to the trace buffer 206 in system memory 36′. Thisis particularly unfortunate, since loss of trace data increases thedifficulty in locating this software error. To prevent this, a tracebuffer protection module 129 (FIG. 2), containing a comparator unit,monitors CPU accesses to system memory 36′, ensuring that any accessesbetween START_ADDRESS and END_ADDRESS will result in halting the CPU 32′through a breakpoint, with the NTAE status bit set.

A system and method in accordance with the present invention lowers thecost of implementing trace features for the microcontroller and for thedebug tools by offering a mechanism to temporarily store data in on-chipmemory, to allow this data to be retrieved at an arbitrarily lowbandwidth via a low speed debug port by the debug tool at a later time.A system and method in accordance with the present invention eliminatesthe need for a dedicated trace port in the device, reduces the size ofthe frame buffer, and eliminates the need for high-speed logic in thedebug tool.

A system and method in accordance with the present invention allows forthe implementation of more powerful trace features in microcontrollerswithout increasing the pin cost of debug features. It also allowsstrongly improved support for third party debug tools with tracecapability, allowing more customers to take advantage ofmicrocontrollers with on-chip trace features.

Although the present invention has been described in accordance with theembodiments shown, one of ordinary skill in the art will readilyrecognize that there could be variations to the embodiments and thosevariations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe appended claims.

1. A microcontroller comprising: a microprocessor; a memory deviceaccessible through a data bus and an address bus coupled to themicroprocessor; on-chip debug logic coupled to the microprocessor; theon-chip debug logic including a low speed debug port; and a mechanismfor temporarily storing trace data on the memory, wherein the trace datacan be retrieved via the debug port by a debug tool.
 2. Themicrocontroller of claim 1 wherein the memory device can reside on-chipor off-chip.
 3. The microcontroller of claim 1 wherein the mechanismincludes a trace extractor module.
 4. The microcontroller of claim 3wherein the trace extractor module includes a plurality of debugregisters which can be configured to determine the behavior of themechanism.
 5. The microcontroller of claim 4 wherein the plurality ofregisters includes a first register (RWA), reflecting the next systemmemory address to be written; a second register collecting frames intobus-sized units; a third register (CNT) for storing the size of thetrace buffer; a fourth register (control) for indicating the actionstaken when the trace buffer is full; and a plurality of statusregisters, wherein each of the plurality of status registers aresingle-bit read-only registers indicating the status of the tracebuffer.
 6. The microcontroller of claim 1 which further includes: anon-chip debug control in communication with low speed debug port and themicroprocessor; a bus monitor coupled to the on-chip debug control, theaddress bus and data bus; a frame buffer in communication with the busmonitor; a trace extractor module in communication with the framebuffer, on-chip debug control and bus monitor; a memory interface incommunication with the trace extractor module; and a bus matrix coupledto the memory interface and for communicating with the system memory; atrace buffer protection module in communication with the on-chip debutcontrol, trace extractor module, and the bus matrix.
 7. Themicrocontroller of claim 6 wherein the trace extractor module comprises:a first register (RWD) for receiving data from the frame buffer inbus-sized units; and providing data to the memory interface; a secondregister (CNT) which provides the size of the trace buffer andcommunicates that data to the trace buffer; a third register forproviding the next memory address to be written; a fourth register forindicating actions to be taken when the trace buffer is full; and aplurality of status registers.
 8. The microcontroller of claim 6 whereinthe comparator module comprises: a comparator identifying illegal CPUaccess to system memory locations within the trace buffer; and abreakpoint generator for halting the CPU when an illegal access iddetected.
 9. The microcontroller of claim 8 wherein a status bitidentifies a breakpoint due to illegal access to the trace buffer.
 10. Amethod for storing and extracting trace information in amicrocontroller, the microcontroller comprising a microprocessor, amemory device accessible through a data bus and an address bus coupledto the microprocessor, on-chip debug logic coupled to themicroprocessor, the method comprising: accumulating trace frames into afirst register until the first register is full; providing the contentsof the first register to the memory device after the first register isfull; and reading out of the memory device the valid trace frames usinga debug port.
 11. The method of claim 10 wherein the valid trace framesare within a trace buffer.
 12. The method of claim 11 wherein tracebuffer is implemented as a circular buffer, thus repeatedly overwrittenby new trace frames until the end of the trace capture sequence.
 13. Themethod of claim 11 wherein a status register indicates that the tracebuffer has been overwritten at least one.
 14. The method of claim 11wherein the trace capture sequence ends when the trace buffer is full.15. The method of claim 14 wherein the CPU receives a breakpoint whenthe trace capture sequence ends.
 16. The method of claim 15 wherein astatus bit identifies the breakpoint issued due to the trace bufferbeing full.